1. Field of the Invention
This invention relates to a non-volatile semiconductor memory device and an electric device with the same.
2. Description of Related Art
A NAND-type flash memory is known as an EEPROM which may be constructed with a large capacity due to that this flash memory is formed by arranging NAND cell units each having plural memory cells connected in series. In such the NAND-type flash memory, data erase is usually performed in a way that one block serves as an erase unit, where one block is defined as a group of NAND cell units arranged in the direction of word lines. Recently, for the purpose of improving data rewrite performance of a flash memory with a large capacity, it has been provided a NAND-type flash memory in which data erase is performed by a page (e.g., refer to Japanese Patent Application Laid Open No. 10-302488).
An EEPEOM such as the NAND-type flash memory has, in general, a complicated peripheral circuit around a memory core circuit which includes cell array, decoder and sense amplifier circuit. The peripheral circuit includes a controller for executing data read control and data write/erase sequence control, command and address circuits which are activated by external timing signals to operate, high voltage generation circuits controlled by the controller to output various high voltages necessary for the respective operation modes, and the like.
The controller in the peripheral circuit is a synchronous circuit which outputs various timing signals as synchronous with a clock output from an internal oscillator. In contrast, the command circuit and address circuit are non-synchronous ones each having an event activated by an external timing signal supplied from external of the chip and another event activated by an internal timing signal output from the controller.
Read operation will be explained in detail bellow. Input a write enable signal WEn, and input command and address data, and the controller is activated. Data read of selected cells is performed under the timing control of the controller. When such the internal data read operation is finished, the controller stops its control operation. Then, input a read enable signal REn from the external, and data output operation is performed for outputting the read data in the sense amplifier circuit to the external of the chip.
In the above-described data read operation, for example, an address counter is incremented in response to the read enable signal REn. At a data write time, the address counter is incremented in response to the write enable signal WEn. On the other hand, there is a prefetch operation for prefetching the read data in the sense amplifier to a data buffer under the control of the controller. In this case, the address counter is incremented synchronously with the internal clock.
The peripheral circuit has, as described above, a complicated configuration including non-synchronous circuits. Especially, in case a multi-value storing scheme, in which one memory cell stores multi-level data, is used, the complexity of the peripheral circuit is more increased. Therefore, there is a large problem that develop period and develop resources of the flash memory are increased.
Usually, a top down designing scheme is adapted to a logic LSI. That is, perform RTL level designing by use of HDL such as Verilog, then generate circuits by a logic composition tool, and a logic LSI may be designed. This scheme, however, may not be applied to the above-described peripheral circuit with non-synchronous circuits in the flash memory as it is.